TARAN: Domain‐Specific Computers in the Post Moore’s Law Era
Energy-efficient and resilient computing architectures through hardware acceleration

Energy efficiency has now become one of the main requirements for virtually all computing platforms. Computer architects are however facing new challenges for the next couple of decades, with the most prominent one being the end of CMOS scaling (Moore's law). Our belief is that the key to sustaining improvements in performance (both speed and energy) is domain-specific computing where all layers of computing, from languages and compilers to runtime and circuit design, must be carefully tailored to specific contexts. In this new age, the processor will be augmented by a bunch of hardware accelerators meant to perform specific tasks in a more efficient way. Our research team focuses on designing accelerators that can prove energy-efficient and fault-tolerant.

Our research topics cover four main challenges:

(1) raising the level of abstraction of accelerator design without sacrificing performance, this includes not only proposing new specialized architectures but also their associated compilers and runtimes; researching methods to build accelerators that (2) compute just right and (3) are resilient to radiation-induced faults or security attacks; and (4) taking advantage of non-conventional, emerging technologies. Another common challenge for the entire team is design space exploration, which has been and will continue to be an essential process for hardware design. We can only expect the design space to keep expanding, and we must persist on developing techniques to efficiently navigate through the design space.