High-Level Synthesis of Instruction Set Processors

This thesis focuses on automatically synthesizing instruction set processors using High-Level Synthesis (HLS). In particular, we aim at automatically generating in-order pipelined processor cores from a high-level description in C in the form of an Instruction Set Simulator (ISS). During our work, we developed a fully-automated hardware design flow that can compile an algorithmic description to speculative hardware, SpecHLS. We propose a set of source-to-source transformations that build on top of speculative loop pipelining to expose control flow and memory speculation opportunities in C code, and we generate speculation-enabled code that can be synthesized using a commercial HLS toolchain. SpecHLS can handle multiple interacting speculations, independent speculations in decoupled hardware modules, and memory speculation. Our work results in an end-to-end processor design flow capable of generating multiple instances of in-order RISC-V processors from an ISS. We show that we can efficiently explore a design space with hundreds of thousands of possible speculative hardware configurations in minutes and generate processor designs competitive with state-of-the-art embedded MCU-class cores.