Hardware Accelerated Simulation and Automatic Design of Heterogeneous Architecture

Vous êtes cordialement invités à venir assister à la soutenance de thèse de CONG Minh Thanh, équipe TARAN, le mercredi 15 mars 2023 à 10h15 en salle Pétri/Turing.

Hardware Accelerated Simulation and Automatic Design of Heterogeneous Architecture

The design of heterogeneous system-on-chip platforms is complex with many possible combinations. Detailed simulation of different solutions is necessary to determine the best design. Existing simulation environments (such as gem5) are limited as they are purely software based and do not take into account heterogeneous architectures. To address these limitations, the use of reprogrammable FPGA components to accelerate simulation is promising. The first part of this thesis is experimental and studies an approach to design heterogeneous architectures focusing on simulating performance models of architecture components (hardware accelerators and processor cores) on FPGA platforms. The second part is methodological and concerns a flow to determine the best microarchitecture in terms of performance to energy consumption ratio. This flow combines a software architecture simulator and a hyperparameter optimization method to find the best combination of parallelism, loop unrolling strategies, and memory interfaces. Experiments were conducted on different problems to determine the most optimal solutions in terms of energy efficiency.