Armor  home page


 
 
VLIW-style architecture 
//-----------------------------------------------------
//   Partial armor model
//-----------------------------------------------------

type sword  is int(32)
type uword  is unsigned(32)

type word = sword | uword

type byte      is int(8)
type u16      is unsigned(16)
type i16       is int(16)

type int5      is int(5)
type unsig5 is unsigned(5)

// ------------------
// Memorization units
// ------------------

// physical resources

mem M (1024 * 32) <access Rd=1 Wr=3 > <addressingUnit = 16>
regFile R(32,word)  <access Rd=1 Wr=2 >

// logical resources

regFile Rs(sword) alias[R]  // signed values
regFile Ru(uword) alias[R]  // unsigned values

// ----------------
// Functional units
// ----------------

fu alu1  <cycle=3>
fu alu2  <cycle=3>
fu alu3  <cycle=3>
fu mp    <cycle=3>

fu alu = alu1 | alu2 | alu3

// -------------------------
// Instruction set structure
// -------------------------

instructionSet = [ DF_nop  || DF_nop || DF_nop || DF_nop ]     |    control

gp DF_nop = dataflow | moveData | nop
gp moveData = load | store | moveReg
gp control = ncBranch | cBranch
 

// ----------------------
// Compute instructions
// ----------------------

gp dataFlow = signedDF |  unsignedDF

df signedDF is      { Rs = operation(Rs,source2_sig) }
df unsignedDF is { Ru = operation(Ru,source2_unsig) }

op operation = sum | difference | mult | compare
op compare = greater | less | lessEq | grtEq | equal | diff

mode source2_sig = Rs | imm(int5)
mode source2_unsig = Ru | imm(unsig5)
 

// --------------------------
// memory access instructions
// --------------------------

df load   is { R = M[ad] }
df store is { M[ad] = R }

//adresses

address ad = immediate | register | indexed

address immediate is imm(u16)                   // @ = imm value
address register    is R                                  // @ = value in R
address indexed     is sum(R,imm(sig5))    // @ = R + immediate offset
 

// -----------------
// move instructions
// -----------------
 

df moveReg       is { R = R }
df moveConstS is { Rs = imm(i16) }
df moveConstU is { Ru = imm(u16) }
 

// --------------------
// control instructions
// --------------------
 

ctr cBranch   is IF c THEN BRANCH(imm(u16))
ctr ncBranch is BRANCH(imm(u16))

cond c is TRUE(R) <ress=uals>
 

// ---------
// Operators
// ---------
 

op sum(x,y)            is   ADD(x,y)   <ress=ual>
op difference(x,y)  is   SUB(x,y)   <ress=ual>
op mult(x,y)            is  MPY(x,y)   <ress=mp>

op greater(x,y)      is   GRT(x,y)      <ress=uals>
op less(x,y)            is   LESS(x,y)     <ress=uals>
op grtEq(x,y)         is   GRT_EQ(x,y)   <ress=uals>
op lessEq(x,y)       is   LESS_EQ(x,y)  <ress=uals>
op equal(x,y)         is   EQ(x,y)       <ress=uals>
op diff(x,y)            is   DIFF(x,y)     <ress=uals> 


charot@irisa.fr- january 1999