VLIW-style architecture |
//-----------------------------------------------------
// Partial armor model //----------------------------------------------------- type sword is int(32)
type word = sword | uword type byte is int(8)
type int5 is int(5)
// ------------------
// physical resources mem M (1024 * 32) <access Rd=1 Wr=3 > <addressingUnit
= 16>
// logical resources regFile Rs(sword) alias[R] // signed values
// ----------------
fu alu1 <cycle=3>
fu alu = alu1 | alu2 | alu3 // -------------------------
instructionSet = [ DF_nop || DF_nop || DF_nop || DF_nop ] | control gp DF_nop = dataflow | moveData | nop
// ----------------------
gp dataFlow = signedDF | unsignedDF df signedDF is { Rs =
operation(Rs,source2_sig) }
op operation = sum | difference | mult | compare
mode source2_sig = Rs | imm(int5)
// --------------------------
df load is { R = M[ad] }
//adresses address ad = immediate | register | indexed address immediate is imm(u16)
// @ = imm value
// -----------------
df moveReg is {
R = R }
// --------------------
ctr cBranch is IF c THEN BRANCH(imm(u16))
cond c is TRUE(R) <ress=uals>
// ---------
op sum(x,y)
is ADD(x,y) <ress=ual>
op greater(x,y) is
GRT(x,y) <ress=uals>
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