An instruction set is described using rules, which form a grammar from which each possible derivation represents one legal instruction.  A description consists of a main  InstructionSet rule (top-level rule) which describes all the alternatives in the instruction set, gp (group) rules allows instructions to be grouped and restriction rules explicit parallelism restrictions to be modeled. The combination of such rules models the set of instructions and the available parallelism. The behavior of each instruction is defined using df rules (data-flow instructions) which correspond to traversals of a data-path unit and ctr rules for control flow instructions.  These rules define register transfers using operators (defined with op and class rules), or lists of operands (mode rules). Processor resources are defined using reg (register), regFile (register file),  mem (memory),  fu (functional unit), etc. rules. Resources are stamped with access and timing information.

Extracts of processor descriptions are given for two different styles:

• VLIW-style architecture
• DSP-style architecture