Tovinakere Dwarakanath Vivek
Research Scholar
CAIRN-INRIA/IRISA Laboratory
ENSSAT, University of Rennes 1
6 rue de Kerampont
22300 Lannion (France)
Welcome to my homepage!
I am a research scholar in CAIRN-the reconfigurable
architectures group of IRISA in INRIA (Bretagne-Atlantique) since September 2009. The theme of the lab is
'Energy Efficient System-on-Chips'. Currently my research interests are in
the ultra-low power design of SoCs. My work forms a part of overall aims
and objectives of GEODES project of Information Technology for European
Advancement (ITEA2) program.
Short Autobiography
I obtained Bachelor of Engineering degree in
Electronics and Communications Engineering from University of Mysore, India in
1998 and Master of Technology in Electrical Engineering with a major in
Microelectronics from Indian Institute of Technology - Kanpur, India in
2001. From 2001 to 2009, I worked for different semiconductor
companies in various roles in ASIC design. From September 2009,
I am working on ultra-low power design techniques for energy
efficient SoCs.
You can find my detailed CV here.
Publications
1.
Vivek D. Tovinakere, Olivier Sentieys and Steven Derrien,
"A Polynomial Based Approach to Wakeup Time and Energy Estimation in
Power-Gated Logic Clusters," Journal of Low Power Electronics,
vol. 7, no. 4, pp. 482-489, Dec. 2011.
2.
Divya Krishna Murthy, Shen Li,
Satoshi Goto, Tomoyashi
Sato and Vivek T.D., "Dynamic Reconfiguration in Motion Estimation,"
in Proceedings of the Asia-South Pacific International Conference on
Embedded SoCs, July 6-7, 2005, Bangalore, India.
Contact
E-Mail: vivektd@irisa.fr
Phone: +33.2.96469181
To network with me please visit my LinkedIn Profile
Coming up...
1. 49th
Design Automation Conference, June 3-7, 2012, San Francisco.
2. Embedded FPGA in
3D-IC technology
Past Events
None