Increasing parallelism reduces power
Vdd (V)
FoM (Hz)
2
1
0
0
F/2
F
Processor
120 MHz
CLK
Vdd = 1.8V
Processor
60 MHz
CLK
Vdd = 0.8V
Processor
60 MHz
CLK
P1 = Cpd * 120 * 1.8 2
P2 = 2 * Cpd * 60 * 0.8 2
Speed = f(V)
Power = f(V^2)
.
Power reduced by 5 for same performance
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