MOVIE

Architecture of the chip

Externally, the MOVIE chip is provided with the following ports:

• four 16-bit data ports to allow MOVIE chips to be easily interconnected,
• three 16-bit video ports to handle data video I/O,
• two instruction ports to send instructions both to the PEc array and to the PEio processor,
• a memory interface port for external memory exchange.

The internal architecture of the MOVIE chip is organized into four main modules. These modules are an array of computation processors, a I/O processor, an instruction decoder and a video I/O controller.

The PEc computation processor is a 16-bit processor that includes a register file unit, a 3-stage pipelined ALU and a 4-port internal memory with their associated address generator units. The ALU allows up to three arithmetic operations to be simultaneously executed through pipelining. A communication operation between PEc can take place in parallel with the arithmetic operation in order to achieve maximum performances and to have a balanced operative part.

The 32-bit PEio processor is based on the same architecture than the PEc processor in order to simplify the work of the code generator. The main difference concerns the local memory which is external in order to allow large capacity (up to 4 MB) if necessary.

The preliminary version of the circuit is targeted to contain 8 PEc processors. Note however that a reconfiguration capability will allow n MOVIE circuits to be clustered so as to act as a single circuit with 8n PEc processors.