Tiling and Scheduling with Architectural and Applicative Constraints

Corinne Ancourt (a), François Irigoin (a), Bertrand Jeannet (b) Jean Jourdan (b), Denis Barthou (c) Juliette Mattioli (b) and Christophe Guettier (a/b)

(a) CRI, Ecole des Mines de Paris, Fontainbleau
(b) LCR, Thomson CSF, Orsay
(a) PRISM, Université de Versailles

This talk presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applications where coarse or medium grain scheduling techniques can be used, DSP applications integrate several thousand of tasks and hence necessitate fine grain considerations. Moreover finding an effective mapping imperatively require to take into account both architectural resources constraints and real time constraints. The main contribution of this paper is to show how it is possible to handle and to solve data partitioning, and fine-grain scheduling under the above operational constraints using Concurrent Constraints Logic Programming languages (CCLP). Our concurrent resolution technique undertaking linear and non linear constraints takes advantage of the special features of signal processing applications and provides a solution equivalent to a manual solution for the representative "BROAD BAND SURVEILLANCE" application.

Further info and related paper(s):

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