Machine Description

This page presents some details of a simplified machine description for the Sparc v7 architecture. They are grouped in four sections as explained in the previous page.

This file is first processed by cpp. This allows us to use #define directives.

1. Syntax of the assembly language

(target "SPARC")

; -- Definition of tokens --
(line_comment_chars "!#")
(comment_chars      "!")
(def_exact ",aS()_[]+-")

#define INT_TOKEN(CHAR)\
    (def_token CHAR [(regex "%[1-2][0-9]\\|\\(%30\\)\\|\\(%31\\)\\|
     %o[0-7]\\|%g[0-7]\\|%l[0-7]\\|%i[0-7]")])
INT_TOKEN("1")   ; rs1 register
INT_TOKEN("2")   ; rs2 register
INT_TOKEN("d")   ; rd register

#define FLP_TOKEN(CHAR)\
    (def_token CHAR [(regex "%f[1-2][0-9]\\|\\(%f30\\)\\|\\(%f31\\)
      \\|%f[0-9]")])             
FLP_TOKEN("e")           ; frs1 floating point register
FLP_TOKEN("f")           ; frs2 floating point register
FLP_TOKEN("g")           ; frd floating point register

(def_token "i" [(read_exp)])

2. Resources List

; floating point registers and floating point status register
(def_ress (base_name "%f" 0 31)	 [(type "reg") (width 32)])
(def_ress (name "fcc") [(type "reg") (width 2)]

; global, "out", local and "in" registers 
(def_ress (base_name "%g" 0 7)	 [(type "reg") (width 32)])
(def_ress (base_name "%o" 0 7)	 [(type "reg") (width 32)])
(def_ress (base_name "%l" 0 7)	 [(type "reg") (width 32)])
(def_ress (base_name "%i" 0 7)	 [(type "reg") (width 32)])

;Functional units
(def_ress (name "mem")	 [(type "memory")])
(def_ress (name "issue") [(type "functional_unit")])
(def_ress (name "alu") [(type "functional_unit")])

3. Instruction Set Description

The instruction set description is typically divided into two parts. The first part lists the complete set of instructions with their associated formats and map them with a reservation table. The second part describes the reservation tables.

Instructions and formats

Description of the instruction add reg + reg -> reg and add reg + imm -> reg: 
(def_asm  "add"   [ (input  "1,2,d")     R_CPU_ALU_3 ])
(def_asm  "add"   [ (input  "1,i,d")     R_CPU_ALU_1 ])
Description of the "branch if not equal": 
(def_asm  "bne" [(input ",al") (sem [S_BRANCH(0) DELAY_SLOT]) R_CPU_B ])

Reservation tables:

#define ISSUE (ress (name "issue") [(use) (at_cycle 1)])

#define R_CPU_ALU_1 \
(reser_table [ \
  ISSUE  \
	(ress (match_arg 0) [(read)  (at_cycle 1) INT_REG]) \
	(ress (name "alu")  [(use)   (at_cycle 2)]) \
	(ress (match_arg 2) [(write) (from_cycle 2) (to_cycle 2) INT_REG]) ])

#define R_CPU_ALU_3 \
(reser_table [ \
  ISSUE  \
	(ress (match_arg 0) [(read)  (at_cycle 1) INT_REG]) \
	(ress (match_arg 1) [(read)  (at_cycle 1) INT_REG]) \
	(ress (name "alu")  [(use)   (at_cycle 2)]) \
	(ress (match_arg 2) [(write) (from_cycle 2) (to_cycle 2) INT_REG]) ])

#define R_CPU_B \
(reser_table [ \
  ISSUE_BRANCH  \
	(ress (name "icc")  [(read)  (at_cycle 1)]) \
	(ress (name "alu")  [(use)   (at_cycle 2)]) ])

4. Semantical Information

#define S_BRANCH(index)	(branch index)
#define DELAY_SLOT	(delay_slot 1)
Erven.