Research Projects > CAPS > Members
|
|
|
|
|
||||||||||||||
contact informationIRISA phone: +33 2 99 84 72 21 e-mail: pvillalo@irisa.fr
Current projectThe objective is to develop the IAOO toolkit : a complete IA64 research environment that acts as a framework for building processor emulator and simulator. In the sametime, Calvin2 and Dice tools are modified to target the IA64 instruction set. Dice is developed as a client of the IAOO framework. Cursus03/2001 to 08/2001 : Internship at Philips NatLab, Eindhoven, The Netherlands. The study approached binary instruction encoding for EPIC architectures. It particularly focused on the inter-action between the instruction encoding and the pipeline decode stages.09/2001 : I obtained a MS CS/ES, option processor architecture,
from Rennes University, France. www.ifsic.univ-rennes1.fr/formation_initiale/diic 07/1998 : I obtained a Bachelor degree in metrology from Nantes
technical University, France. www.univ-nantes.fr/jsp/fiche_structure.jsp?STNAV=921&CODE=92130
|
|||||||||||||||
|
|||||||||||||||
