TRUONG Nam Dan, Ph.D.

Computer architect working on memory hierarchy performance evaluation and optimization. Searches for new solutions in hardware, software, compilation or OS memory management. Has interests among other things in high performance processors, low power embedded systems, optimizing compilers, memory management and OSes, performance evaluation and performance tuning tools, Java, Internet...

Employment

CS Teaching assistant, University of Rennes 1, France 1998 - Sept. 1999

• Taught Mathematica classes
• Supervised the final project of 4 MS student (out of campus)
• Researcher at the IRISA, in the CAPS team (Compilation, Parallel Architectures and Systems).
• Developed M2C, a multi-cache configuration simulation environment (tracing, simulation, visualization).

EE Teaching assistant, ENSSAT of Lannion, France 1997 - 1998

• Taught EE students EE and CS classes, supervised 3 month projects
• Researcher at the LASTI, in the Architecture group.

PhD in CS, University of Rennes 1, France 1994 - 1998

The goal was to develop software data layout optimization techniques to improve cache performance. The focus was on non-numeric applications written in high level languages like C.
The work was done at the IRISA (INRIA), supervised by André Seznec and François Bodin. The Jury was further composed of Jean Pierre Banâtre, Daniel Etiemble, Daniel Litaize and Olivier Sentieys.

• Developed Ialloc, an allocation library to support layout optimizations, distributed freely by INRIA
• Reviewer for Europar'96, Micro-29 and ISCA'96
• President of the ADOC association of PhD students in 1996
• Member of the organizing board of RD-96 & RD-97, a local workshop for PhD students
• Web master of the CAPS research team and the ADOC from 1995 to 1997
• Followed a summer school in architecture, as well as an oral and a job search formations

PC computer administrator, French Embassy of Bangui, C.A.R. 1992 - 1994

• Free-lance maintenance for private companies
• French observer during the C.A.R. presidential elections at the Commission Electorale Mixte

MS projects in VHDL 1992 - 1994

• Specification of Rapid-2 a content addressable memory for database searches.
• Semi-custom design of a 32-bit version of the AMD2901 using data path generators.
• Development of a 4-bit AMD2901 using standard-cells, was sent to foundry.

Education

PhD in CS, honors, University of Rennes 1, France 1998

MS in EE, honors, University of Paris 6, France 1992
Major : architecture of integrated circuits

BS in EE, honors, University of Paris 6, France 1990

French Baccalauréat, Lycée Français International, MD, USA 1986
Major : Mathematics and sciences (Bac. C)

High School Diploma, MD, USA 1985

Languages

French native,

English fluent (667 score TOEFL, 4 years in USA),

Spanish scholar.

Skills

Computer languages : C, C++, Mathematica, Pascal, Visual Basic, Assemblers, HTML, JavaScript, plus notions in Java, Matlab, VHDL, dBase IV...

Comfortable with most standard software tools

Electronics : computer architecture, digital, FPGA, analog, electricty, soldering...

Stock market : French stock exchange

Notions of mechanics, industrial sketching, physics, biology...

Publications

1. M2C, a multi-cache configurations simulation environment, D. Truong
   Not yet available, preliminary example at http://www.irisa.fr/caps/PEOPLE/Dan/M2C

2. Optimisations logicielles de la localité : le placement précis des données en mémoire
   PhD dissertation, order number 2040, University of Rennes 1, France, Sept. 1998.

3. Ialloc 1.0, a dynamic allocation library supporting data layout optimizations, D. Truong
   Available at http://www.irisa.fr/caps/PEOPLE/Dan/Ialloc

4. Improving Cache Behavior of Dynamically Allocated Data Structures, D. Truong, F. Bodin, A. Seznec,
   PACT'98, IEEE International Conference on Parallel Architecture and Compilation Techniques, Paris, France, Sept. 14-18, 1998.

5. Considerations on Dynamically Allocated Data Structure Layout Optimization, D. Truong,
   PFDC-1, Workshop on Profile and Feedback-Directed Compilation, Paris, France, Sept. 12, 1998.

6. Accurate data layout into blocks may boost cache performance, D. Truong, F. Bodin, A. Seznec,
   Interact-2, Second IEEE workshop on Interaction between Compilers and Computer Architecture, San Antonio, TX, Feb. 1st, 1996.