« Enlarging » the instruction window (supported by Intel)
In an O-O-O processor, fireable instructions are chosen in a window of a few tens of RISC-like instructions.
Limitations are:
- size of the window
- number of physical registers
Prescheduling:
- separate data flow scheduling from resource arbitration.
- coarser units of work ?
Reducing the number of physical registers:
- how to detect when a physical register is dead ?
- Per group validation ? revisiting CISC/RISC war ?